As is known in the art, typical amplifiers have an input terminal for receiving an AC input signal; and, an output terminal where an amplified AC signal is produced as an output signal, as shown in FIG. 1. The relationship between the input signal power Pin and the produced output signal power Pout is indicated by curve A in FIG. 6. It is noted that in a linear operating region of the amplifier, the signal produced by the amplifier at the output terminal is directly proportional to the input signal; and, that in a non-linear region, the output signal is not directly proportional to the input signal. It is also noted that in a high input signal power region of the non-linear region the amplifier operates in a compression region (Pout=Pout_comr_A) where the output power signal is inhibited from increasing with an increase in the input signal. Thus, the compression operating region is a region where the amplifier produces its maximum output power.
More particularly, and considering here for example, a Field Effect Transistor (FET) amplifier, the FET (FIG. 1) is arranged in a conventional grounded source (S) configuration, having the input signal fed to the gate (G) of the FET through an AC coupling capacitor, and a drain (D) being AC coupled to an output terminal to provide an amplified output signal. A gate voltage Vgg is provided by a POWER SUPPLY 1 producing a voltage Vdc1=Vgg and a gate current Igg. A drain current, Idd, is supplied by a POWER SUPPLY 2 producing voltage Vdc2. The operating region of the FET is a function of: the power level of the input signal; and, a DC bias condition (DC bias current and/or voltage) applied to the FET from POWER SUPPLY 1 and POWER SUPPLY 2.
The FET has a predetermined quiescent operating state or Q-point established by the DC bias voltage level and current level fed to the FET. The quiescent point, or Q-point, is the steady-state (DC) voltage or current at a specified terminal of an active device (here the FET) with no input signal. The quiescent point is selected to achieve optimal performance in both linear and non-linear regions. One critical amplifier performance parameter in the linear region is 3rd Order Intercept Point (IP3) which measures amount of 3rd order distortions (intermodulations) that amplifier produces on its output when fed by an input signal containing two or more independent frequency tones. One critical amplifier performance parameter in the non-linear region is compressed output power (Pout_comr) which measures maximum power that the amplifier is capable of producing at its output terminal when fed by an input signal containing one frequency tone.
With such an amplifier, when the input signal power increases so that the amplifier transitions from linear into non-linear regions, a DC current drawn by the amplifier from a DC bias power supply increases above the quiescent current IQ (as indicated by curve A in FIG. 7) and the power in the output signal correspondingly increases until the amplifier reaches the compression operating region and produces a maximum output power level Pout=Pout_comr_A as shown in a curve A in FIG. 6. It is noted that there is nothing in the amplifier circuit of FIG. 1 that limits the amount of current Idd drawn by the amplifier from the POWER SUPPLY (FIG. 1). It is also noted that in this case, Vdd=Vdc2, as shown by curve A in FIG. 8.
In many receiver amplifier systems, there is a need to limit the maximum output power, Pout_comr, of the system below the output power produced by a stand-alone amplifier that operates in its compression region, Pout_comr_A. This needs to be accomplished without degrading the amplifier's linearity (often measured by IP3) when the amplifier operates in its linear region. In a typical amplifier, Pout_comr is strongly correlated with the IP3. Therefore, it is in some applications, desirable to modify amplifier behavior in a way that affects only its non-linear region's characteristic (Pout_comr), but not its linear region's one (IP3).
One technique used to solve this problem is a feedback or closed loop-control amplifier system, such as shown in FIG. 2. Here, a detector is placed somewhere within the signal path of the amplifier (at the input signal path to the amplifier, inside the signal path of the amplifier itself, or in the output signal path of the amplifier). When the signal becomes sufficiently large, the detector actuates a switch in the signal path (either internal or external to the circuit) to disconnect the circuit's output from downstream elements of the system. Alternatively, the detector may control the DC bias of the circuit to affect its output power. One problem with this technique is that it requires extensive control theory analysis to ensure its stability. The second problem is finite response time, i.e., time interval between signal becoming large enough and the switch being actuated. The third problem is that the system's linear region linearity is adversely affected by the switch's insertion loss, because it is situated in the AC signal path.
Another technique is to place a nonlinear component in the signal path as shown in FIG. 3. This component has a low insertion loss at low signal levels and high insertion loss above a predetermined threshold level. Once the circuit's output power exceeds this threshold level, its output power becomes limited by the high insertion loss of the limiter. With such an arrangement, however, the limiter's insertion loss in the low-power regime has negative effects on the circuit's linearity and gain, and, in the high power regime the limiter reflects AC signal at its input that may cause circuit instability and/or channel temperature increase of a transistor within the amplifier.
Another common technique that accomplishes the output power limiting is shown in FIG. 4. Here, a constant current source (active load) is connected between the DC POWER SUPPLY 2 and the drain of the FET amplifier to produce a constant DC current IQ, both under the quiescent condition and with an input AC signal present. The amplifier draws this constant current independent of the input signal power level, as shown in the curve labeled B in FIG. 7. Thus, here Vdc1=Vgg and Vdc2>Vdd, where Vdc2 is the voltage produced by POWER SUPPLY 2 and Vdd is the voltage at the drain of the amplifier. The curve B in FIG. 6 shows the relationship of output power vs. input power for the circuit of FIG. 4. It is being noted that the output power of the amplifier shown in FIG. 4 is lower than the output power of the amplifier shown in FIG. 1, that is Pout=Pout_comr_B<Pout_comr_A. In this arrangement, however, for the circuit to operate in a constant current mode the voltage drop across the constant current source VCCS,q=(Vdc2−Vdd) has to be larger than knee voltage Vknee, (the voltage at which the linear region transitions to the non-linear region), as shown in FIG. 10. This voltage drop across the constant current source lowers the quiescent voltage level at the Vdd terminal of the amplifier as shown in the curve B in FIG. 8. As known in art, this lower quiescent voltage leads to lower DC power available to the amplifier, which, in turn, results, in degraded amplifier's IP3.